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We are looking for a senior verification engineer for the Multimedia IP team in Taiwan. The team is involved in IP developments for multiple SOC product lines. In this position, you will have the chance to work on multimedia IP's for our SOC chips.

What you will be doing:

• Verification of our display subsystem/IP.

• Work with Architect, Design, SOC teams to define verification scope, strategies, test planning, and verify designs at both block level and full chip level.

• Develop verification infrastructure.

What we need to see:

• Masters Degree in EE, CS or CE or equivalent work experience.

• 3+ years of industry experience.

• Proficiency with System Verilog, UVM, C/C++.

• Experience with verification of multimedia IP at block level, subsystem level, or full chip level.

• Deep understanding of verification concepts.

• Outstanding analytical skills and problem-solving skills.

• Good written and verbal communication skills.

Ways to stand out from the crowd:

• Experience with verification of display subsystem/IP.

• Familiarity with SoC concepts such as CPU, memory, interconnects, clock/reset, security, etc.

• Ability to analyze architecture and micro-architecture spec and define test plan.

• Experience in writing C++/SystemC models.

• Proficient scripting experience in Python, Perl, tcl, Make, shell.

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